This disclosure relates to microfabrication including microfabrication of integrated circuits.
Semiconductor manufacturing includes various patterning processes including deposition, photolithography, etching, planarization, doping, etc. These patterning processes are repeated as structures are created, modified and removed. Photolithographic and other patterning processes typically benefit from a planar surface for depositing the various films and resists used to pattern and form structures on a wafer. Films can be specified to have a particular height and/or be planarized to within certain dimensions, depending on a given fabrication process.
Planarization is commonly performed using a process known as Chemical Mechanical Polishing (CMP). CMP is a process that uses corrosive chemicals and a polishing pad to planarize the surface of a wafer, similar to how wet sanding works. CMP can planarize insulators and conductors in multilevel structures. This planarization can be used to stack more electronics onto another layer of a wafer, or to planarize the wafer for subsequent photo lithographic patterning.